Presentation
Expediting UCIe and Boot Verification using Distributed Ndie Simulations and Emulation for Multi-Chiplet AI SoCs
DescriptionWith the emergence of complex multi-die SoC designs, the challenges in verification have increased manifold. This involves integration of pre-verified IPs, sub-systems, and partially verified chiplets using multiple vendor simulator platforms and Verification IPs. Artificial Intelligence (AI) is at the forefront of ASIC breakthroughs. With time to market being a critical factor, adherence to aggressive schedules has become the new normal. Rebuilding these complex verification environments onto a multi-die SoC testbench in the given timelines is extremely challenging. Universal Chiplet Interconnect Express (UCIe) is an open industry standard, multi-protocol, high-bandwidth (up to 32GT/s per lane), die-to-die (chiplet) interconnect that standardizes inter-die communication on-package. The Simulator Independent Verification Platform Development (SIVPD) being vendor agnostic not just addresses the issues at hand but also potentially makes use of licenses in most effective way and results in reduction of both development cycle time and saves the precious license cost. Significant performance and capacity improvements are observed while verifying UCIe using SIVPD with NDIE distributed simulation technology on a 2.5DIC for High Performance Compute (HPC) AI training and inference applications. When compared to traditional UCIe DUT back-to-back setup in a single die testbench, distributed simulation setup has drastically reduced the overall testbench development time and also helped in achieving 3x improvement in simulation speed and flexibility to make this solution ubiquitous for chiplet based architectures. The current SoC consists of 4 homogeneous 4nm chiplets on a single interposer communicating with each other via UCIe 1.1 protocol, QSPI and GPIOs. All 4 dies runs a separate simulation thread on a different LSF machine thereby optimizing the memory requirements to simulate the whole quad-chiplet package together. Emulation further helped in achieving 1000x faster closure of multi-chiplet boot use-cases.
Event Type
Engineering Presentation
TimeTuesday, June 243:45pm - 4:00pm PDT
Location2010, Level 2
AI
Front-End Design
Chiplet