Presentation
Optimized Digital Design Flow for Embedded Sensor Applications Using High Level Synthesis
DescriptionIntegrating algorithms into sensors poses a significant challenge for designers. Technological nodes are chosen for analog requirements, leaving limited space for digital portion, which can not take advantage from technology scaling. Digital designers are challenged with implementing on ASIC high-quality algorithms in terms of accuracy while minimizing area and power consumption. Our proposal introduces a flow based on modular blocks called "Bricks", which have both SystemC and Python views. This approach allows the analysis of how to best connect and configure these Bricks using Python libraries, while also providing feedback to the High-Level Synthesis (HLS) tool. This Python-HLS loop optimizes power, area, latency, and accuracy in a multi-objective optimization process. The proposed flow reduces time to market and enables the best choice among various options. By leveraging the use of Python the flow offers flexibility and configurability, allowing for the utilization of a wide range of libraries and tools. Continuous feedback to the HLS tool facilitates rapid iterations and incremental improvements.
The results in a specific case for a people counter on an infrared image sensor demonstrate the effectiveness of the flow in providing excellent solutions in terms of both accuracy and area, significantly reducing the IP development time.
The results in a specific case for a people counter on an infrared image sensor demonstrate the effectiveness of the flow in providing excellent solutions in terms of both accuracy and area, significantly reducing the IP development time.
Event Type
Engineering Presentation
TimeMonday, June 232:00pm - 2:15pm PDT
Location2010, Level 2
AI
IP
Chiplet