Presentation
Balancing Performance and Side-Channel Resilience in a Lightweight ECC Cryptosystem
DescriptionBinary polynomial multipliers significantly influence the performance and cost efficiency of elliptic curve cryptography (ECC) systems. ECC hardware commonly uses multiplication algorithms with sub quadratic complexity to minimize area usage and enhance speed. This research shows a new type of scalar point multiplication (SPM) processor for elliptic curves that uses a special group of overlap-free multipliers that work best for Internet of Things (IoT) uses. We design these multipliers to reduce partial products and employ overlap-free reconstruction methods, resulting in improved computational recurrence and enhanced efficiency.
The designed ECC-Multiplier can be vulnerable to power side channel leakage analysis if the RTL code has not been validated by thorough security analysis. Through an automated power side-channel leakage verification and root-causing flow, we demonstrated how to find the time and RTL gate with side-channel leakage of a unprotected ECC design. This flow can help ECC designers assess the most secure implementation and fix any leakage gate at early-stage RTL design phase.
The designed ECC-Multiplier can be vulnerable to power side channel leakage analysis if the RTL code has not been validated by thorough security analysis. Through an automated power side-channel leakage verification and root-causing flow, we demonstrated how to find the time and RTL gate with side-channel leakage of a unprotected ECC design. This flow can help ECC designers assess the most secure implementation and fix any leakage gate at early-stage RTL design phase.
Event Type
Engineering Presentation
TimeWednesday, June 2510:30am - 10:45am PDT
Location2010, Level 2
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