Presentation
Late Breaking Results: In-Memory Arithmetic: Enabling Division with Stochastic Logic
DescriptionDesigning an efficient arithmetic division circuit has long been a significant challenge. Traditional binary computation methods rely on complex algorithms that require multiple cycles, complex control logic, and substantial hardware resources. Implementing division with emerg- ing in-memory computing technologies is even more challenging due to susceptibility to noise, process variation, and the complexity of binary division. In this work, we propose an in-memory division architecture leveraging stochastic computing (SC), an emerging technology known for its high fault tolerance and low-cost design. Our approach utilizes a magnetic tunnel junction (MTJ)-based memory architecture to efficiently execute logic-in-memory operations. Experimental results across various process variation conditions demonstrate the robustness of our method against hardware variations. To assess its practical effectiveness, we apply our approach to the Retinex Algorithm for image enhancement, demonstrating its viability in real-world applications.
Event Type
Late Breaking Results
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby