Presentation
Breaking the Design Automation Mold; Wild and Crazy Ideas for Global Optimization
DescriptionSilicon design is complex and expensive with high penalties for iterations. From start to finish, chip implementation has teams of 100s to 1000s of Engineers, geographically distributed across multiple time zones, and spans multiple years of development time. A typical design process goes through 100s of tools in the front end ( from concept to tape-out ) and an equally excruciating process in the back end (from silicon to product release). Silicon development costs have skyrocketed with the shrinking geometries - from sub-hundred million to above $500million.
The complexity and efficiency of Silicon design process has of course been constantly studied. Take for example this survey conducted by Siemens & Wilson Research, which presents a study on Functional Verification. Functional verification has been a key focus for the industry - EDA leaders such as Synopsys, Cadence and Siemens have produced state of the art verification tools.
More recently, Nvidia has demonstrated that use of GenAI can bring significant efficiencies to the Silicon design process.
While there is heavy focus on productivity improvements in specific areas of Silicon Design, the question that remains is what can be done to make the entire design process more efficient. Needless to say, improving efficiency has a significant impact on the industry as a whole - it can reduce the time to market and enable the industry to produce more silicon, faster and cheaper… and this can be a winner for the whole tech industry as Silicon is at the foundation of all technology driving the AI revolution!
Silicon & Hardware Systems designs have significant similarities in process and efficiency challenges. Most people find the HW Systems design to be an extension of the process used in Silicon design making solutions for efficiency mutually beneficial.
The complexity and efficiency of Silicon design process has of course been constantly studied. Take for example this survey conducted by Siemens & Wilson Research, which presents a study on Functional Verification. Functional verification has been a key focus for the industry - EDA leaders such as Synopsys, Cadence and Siemens have produced state of the art verification tools.
More recently, Nvidia has demonstrated that use of GenAI can bring significant efficiencies to the Silicon design process.
While there is heavy focus on productivity improvements in specific areas of Silicon Design, the question that remains is what can be done to make the entire design process more efficient. Needless to say, improving efficiency has a significant impact on the industry as a whole - it can reduce the time to market and enable the industry to produce more silicon, faster and cheaper… and this can be a winner for the whole tech industry as Silicon is at the foundation of all technology driving the AI revolution!
Silicon & Hardware Systems designs have significant similarities in process and efficiency challenges. Most people find the HW Systems design to be an extension of the process used in Silicon design making solutions for efficiency mutually beneficial.
Organizer
Panel Moderator
Event Type
DAC Pavilion Panel
TimeTuesday, June 242:00pm - 2:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall