Presentation
Building Secure Chips Without Jeopardizing Design Budgets and Schedules
DescriptionThe importance of proactively securing semiconductor chips during the design phase has grown significantly over the past few years, driven by the rapidly increasing number of discovered chip security vulnerabilities, emerging industry standards, and new regulations and laws, among other factors. As a result, most would agree on the importance of a robust hardware security program and that security signoff should become another key checkbox before tape-out. Yet, translating this objective into reality is challenging due to tight tape-out schedules, lack of broad security knowledge, limited engineering resources, and the need for new cross-organizational coordination.
This panel of leading hardware security practitioners will discuss the various challenges of securing chips and share how to overcome them in practice, all while staying on schedule, within budget, and boosting competitiveness.
This panel of leading hardware security practitioners will discuss the various challenges of securing chips and share how to overcome them in practice, all while staying on schedule, within budget, and boosting competitiveness.
Event Type
DAC Pavilion Panel
TimeTuesday, June 244:00pm - 4:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall