Presentation
G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
DescriptionThe increasing complexity of high-frequency circuits calls for efficient and accurate passive macromodeling techniques.
Existing passivity enforcement methods, including those in commercial tools, often encounter convergence issues or compromise accuracy.
The Domain-Alternated Optimization (DAO) framework seeks to restore accuracy through an additional optimization step but is hampered by high memory consumption and slow convergence, particularly for large-scale problems.
This paper presents \ours, a novel GPU-accelerated framework that recasts the passivity-enforced macromodeling problem as a neural network training task.
This approach significantly enhances both the speed and scalability of passivity enforcement.
Experimental results show that \ours achieves an average speedup of 7.63$\times$ in convergence compared to DAO, while reducing memory usage by two orders of magnitude.
This enables \ours to handle complex, high-port-count circuits with greater accuracy and efficiency, paving the way for robust high-frequency circuit simulations.
Existing passivity enforcement methods, including those in commercial tools, often encounter convergence issues or compromise accuracy.
The Domain-Alternated Optimization (DAO) framework seeks to restore accuracy through an additional optimization step but is hampered by high memory consumption and slow convergence, particularly for large-scale problems.
This paper presents \ours, a novel GPU-accelerated framework that recasts the passivity-enforced macromodeling problem as a neural network training task.
This approach significantly enhances both the speed and scalability of passivity enforcement.
Experimental results show that \ours achieves an average speedup of 7.63$\times$ in convergence compared to DAO, while reducing memory usage by two orders of magnitude.
This enables \ours to handle complex, high-port-count circuits with greater accuracy and efficiency, paving the way for robust high-frequency circuit simulations.
Event Type
Research Manuscript
TimeMonday, June 2311:15am - 11:30am PDT
Location3006, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test