Presentation
Squeezing Out Hidden Margins for Hard-to-Solved IR Violations in VLSI by Extracting Timing Slack Methodology
DescriptionVoltage drop in the design is always one of the serious concerns which may degrade the performance or lead to the unexpected functional failure. To prevent the risk from the voltage drop, the most common and intuitive method is to reduce the current demand of IR-hotspot instances by downsizing the driving strength or swapping to a slower device with higher threshold voltage. However, reducing the current demand of IR-hotspot instances highly relies on the positive timing slacks remaining on the paths. In other words, if the timing slack is exhausted, such IR-hotspot instance cannot be sized down and becomes a hard-to-solved IR violation. In this paper, Extracting Timing Slack (ETS) methodology is proposed to squeeze out hidden timing slacks for the IR-hotspot instance from its fan-in and fan-out cones. Experimental results show that ETS provides 34% more IR fixing rate compared to the traditional methods.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby