Presentation
PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification
DescriptionAs process nodes advance to sub-5nm technologies, post-layout simulations for integrated circuits have become increasingly complex, with billions to trillions of nodes. The growing design complexity and transistor integration require more accurate and efficient post-layout SPICE simulations. However, existing methods for solving large-scale post-layout circuits face significant challenges due to high computational costs. In this paper, we propose a new approach, PiSPICE, which utilizes adjoint sensitivity analysis to identify critical parasitics and eliminate non-critical ones, effectively reducing the simulation scale and improving speed. By modeling parasitics and performing sensitivity analysis on pre-layout circuits, we significantly reduce the computational burden and avoid the overhead of directly analyzing sensitivities in large-scale post-layout circuits. By retaining only the critical parasitics and apply model order reduction to minimize their impact, while eliminating non-critical parasitics, PiSPICE achieves a maximum 17.27x speedup in simulation with an error margin of less than 0.78% compared to the commercial simulator Spectre.
Event Type
Research Manuscript
TimeWednesday, June 251:30pm - 1:45pm PDT
Location3003, Level 3
EDA
EDA6: Analog CAD, Simulation, Verification and Test