Presentation
Compact Thermal Model-Based Analytical 3D Chip Placement with GPU Acceleration
DescriptionAs the semiconductor industry approaches the physical limits of Moore's Law, 3D integrated circuits (ICs)---which stack multiple dies vertically to improve performance and area efficiency---have emerged as a promising path forward.
However, this stacked architecture brings significant thermal challenges due to restricted heat dissipation.
Early-stage optimization during the placement stage is critical for alleviating these thermal issues.
Yet, existing 3D placement algorithms either fail to incorporate adequate thermal considerations or optimize each die in isolation, underscoring the necessity for a native-3D, thermal-aware, cross-die optimization solution.
In this paper, we propose T3DPlace, which incorporates multiple objectives---including wirelength, density, and thermal---into an analytical framework for cross-die optimization of 3D ICs.
To specifically tackle the unique thermal challenges in 3D ICs, we propose a compact thermal model (CTM)-based objective term, which is accurate and differentiable, seamlessly integrating hotspot temperature optimization into the analytical placement framework.
We implement the proposed framework with GPU acceleration.
Experiments demonstrate that T3DPlace achieves an average hotspot temperature reduction of $30.7\%$, while maintaining the quality of other critical design metrics.
The source code will be publicly accessible at https://github.com/OpenAfterReview.
However, this stacked architecture brings significant thermal challenges due to restricted heat dissipation.
Early-stage optimization during the placement stage is critical for alleviating these thermal issues.
Yet, existing 3D placement algorithms either fail to incorporate adequate thermal considerations or optimize each die in isolation, underscoring the necessity for a native-3D, thermal-aware, cross-die optimization solution.
In this paper, we propose T3DPlace, which incorporates multiple objectives---including wirelength, density, and thermal---into an analytical framework for cross-die optimization of 3D ICs.
To specifically tackle the unique thermal challenges in 3D ICs, we propose a compact thermal model (CTM)-based objective term, which is accurate and differentiable, seamlessly integrating hotspot temperature optimization into the analytical placement framework.
We implement the proposed framework with GPU acceleration.
Experiments demonstrate that T3DPlace achieves an average hotspot temperature reduction of $30.7\%$, while maintaining the quality of other critical design metrics.
The source code will be publicly accessible at https://github.com/OpenAfterReview.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby