Presentation
ADVISOR: Approximate Computing-frienDly High-LeVel Synthesis DesIgn Space ExplORer
DescriptionApproximate computing is a relatively new computing paradigm that allows to trade-off area/power with the accuracy at the outputs. Another relatively new VLSI design trend is to raise the level of design abstraction from the Register-Transfer Level (RTL) to the behavioral level and use High-Level Synthesis (HLS) to synthesize these behavioral descriptions. HLS has one unique advantage over RT-level design. It completely decouples the functional description from the implementation. This allows to design and verify the behavioral description once,
but then generate a large number of hardware implementations of unique area vs. performance trade-offs. This is typically achieved through synthesis directives in the form of pragmas that the HLS user annotates at the source code to mainly control how to synthesize arrays (RAM, registers, expand), loops (unroll, pipeline) and functions (inline or not).
In this work we leverage this uniqueness and build an automated HLS design space explorer to find the hardware circuit most amenable to approximate computing, this is, has the highest potential for area/power savings. We have coined this explorer ADVISOR. The main problem with traditional exploration processes is that their long run time, which is even more accentuated in this case because every new implementation needs to be fully approximated to fully understand the trade-offs in terms of area/power vs. error of each design. Thus, in order
to accelerate this exploration process, we propose to evaluate each new designs based on an Approximation Friendliness Index (AFI) that can be computed statically, very fast, and only fully approximate the designs recommended by our flow that have high AFI values. Experimental results show that this approach leads to basically the same results as exhaustively approximating every new design, while being on average 68× faster.
but then generate a large number of hardware implementations of unique area vs. performance trade-offs. This is typically achieved through synthesis directives in the form of pragmas that the HLS user annotates at the source code to mainly control how to synthesize arrays (RAM, registers, expand), loops (unroll, pipeline) and functions (inline or not).
In this work we leverage this uniqueness and build an automated HLS design space explorer to find the hardware circuit most amenable to approximate computing, this is, has the highest potential for area/power savings. We have coined this explorer ADVISOR. The main problem with traditional exploration processes is that their long run time, which is even more accentuated in this case because every new implementation needs to be fully approximated to fully understand the trade-offs in terms of area/power vs. error of each design. Thus, in order
to accelerate this exploration process, we propose to evaluate each new designs based on an Approximation Friendliness Index (AFI) that can be computed statically, very fast, and only fully approximate the designs recommended by our flow that have high AFI values. Experimental results show that this approach leads to basically the same results as exhaustively approximating every new design, while being on average 68× faster.
Event Type
Research Manuscript
TimeWednesday, June 252:30pm - 2:45pm PDT
Location3004, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis