Presentation
Speeding Up Global Placement Method by Integrating a Precorrected FFT Solver
DescriptionGlobal placement is essential for high-quality and efficient circuit placement, particularly in complex modern VLSI designs. Recent advancements, such as electrostatics-based analytic placement, have improved scalability and solution quality. This work demonstrates that using the precorrected FFT technique for electric field computation significantly reduces runtime. Experimental results on standard benchmarks show a 2.73x speedup in FFT computation and a 29% total runtime improvement against a conventional-FFT-based approach, and a 1.0% reduction of scaled half-perimeter wirelength after detailed placement, paving the way for efficient global VLSI placement.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby