Presentation
NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
DescriptionThis paper introduces Natural-Level Synthesis (NLS), an innovative approach for generating system-level hardware descriptions using generative artificial intelligence (Gen AI). NLS bridges a gap in current hardware development processes, where algorithm engineers' involvement typically ends at the requirements stage. With NLS, engineers can participate more deeply in the development, synthesis, and test stages by using Gen AI models to convert natural language descriptions directly into Hardware Description Language (HDL) code. This approach not only streamlines hardware development but also improves accessibility, fostering a collaborative workflow between hardware and algorithm engineers. We developed the NLS tool to facilitate natural language-driven HDL synthesis, enabling rapid generation of system-level HDL designs while significantly reducing development complexity. Evaluated through case studies and benchmarks using Performance, Power, and Area (PPA) metrics, NLS shows its potential to enhance resource efficiency in hardware development. This work provides a scalable, efficient solution for hardware synthesis and establishes a Visual Studio Code (VS Code) extension to assess Gen AI-driven HDL generation, laying a foundation for future advancements in electronic design automation (EDA).
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby