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Analytical Optimization for Robust and Efficient Analog IC Design Automation
DescriptionThis article presents a methodology to automatically and optimally design and size analog circuits through an analytically derived objective function and constraints based on given specifications, implement their layout, and produce the corresponding Graphic Data System (GDS) files. To implement this flow, a python implementation of the C/ID methodology is used for technology characterization and lookup tables (LUTs) generation. An open source layout generation platform is used for producing circuit layout from an optimized design in an automatized flow. To adequately implement the flow, a method to analyze complexity of circuit networks, and the concept of ``reducibility of problem dimension" is provided. An analytical approach is proposed to formulate a general and technology-agnostic optimization process that is expandable to high degrees of dimensionality for a wide variety of various circuit topologies, accounting for process and temperature variations while maintaining low computational complexity and high accuracy with no simulation iterations required. The methodology and approach affords the ability for clear visualization of design space and and optimums. From this analysis, technology-agnostic topology factors, compute complexity degree, and design scripts will be derived. A case study on a Current Mirror Operational Transconductance Amplifier (CM OTA) illustrates the approach, showing optimal design points for power minimization. The process includes SPICE simulation, layout generation via the ALIGN analog layout generator, and an example using open source Electronic Design Automation (EDA) tools and Skywater's 130~nm design kit, with results compared across analysis, schematic, and post layout netlist simulations. All results, designs, and scripts are publicly available for transparency and easy reproducability.