Presentation
Fast Simulation Algorithm for Negative-Capacitance FinFET Based on Latency Insertion Method
DescriptionFinFET technology has been steadily replacing the traditional MOSFET in sub-20 nm IC devices, due to its low power consumption and excellent scaling characteristics. However, scaling FinFETs beyond 3 nm is challenging. To pursue better power efficiency and performance, the negative capacitance FinFET (NC-FinFET) has been introduced by adding an extra ferroelectric layer at the gate. In this paper, we propose a fast simulation algorithm for NC-FinFETs based on the Latency Insertion Method (LIM). By integrating the BSIM-CMG model and the Landau-Khalatnikov Ferroelectric model, the proposed algorithm achieves orders of magnitude in speedup over conventional circuit simulators for large-scale examples.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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