Presentation
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
DescriptionAbstract—In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology independent optimization. Recent studies have introduced equality saturation as a novel optimization approach. However, its efficiency remains a hurdle against its wide adoption in logic synthesis. This paper proposes a highly scalable and efficient framework named E-morphic. It is the first work that employs equality saturation for resynthesis after conventional technology-independent logic optimizations, enabling structure exploration before technology mapping. Powered by several key enhancements to the equality saturation framework, such as direct e-graph-circuit conversion, solution-space pruning, and simulated annealing for e-graph extraction, this approach not only improves the scalability and extraction efficiency of e-graph rewriting but also addresses the structural bias issue present in conventional logic synthesis flows through parallel structural exploration and resynthesis. Experiments show that, compared to the state-of-the-art delay optimization flow in ABC, E-morphic on average achieves 12.54% area saving and 7.29% delay reduction on the large-scale circuits in the EPFL benchmark.
Event Type
Research Manuscript
TimeTuesday, June 243:45pm - 4:00pm PDT
Location3006, Level 3
EDA
EDA5: RTL/Logic Level and High-level Synthesis