Presentation
High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References
DescriptionThis article proposes a multi-bit in-memory computing array using energy/area-efficient (1146 TOPS/W, 27 TOPS/mm2) in-memory ADC (IMADC) with Cascoded bit-cell. It increases throughput (1.9X) and linearity (23X) compared to input pulse-width modulation by using bit-slicing (BS) with charge-sharing based analog accumulator. Compared to conventional BS with digital accumulation after ADC, this method has better energy-efficiency (1.7X) and throughput (6.6X). Our IMADC is robust to temperature variation and area overhead is merely 3%. This approach achieves accuracy of 97.1% for the MLP (3/2/3b) on MNIST, 91.9% for the VGG-8 (4/2/4b) on CIFAR-10 and 83.8% for GAT (7/3/7b) on Cora.
Event Type
Research Manuscript
TimeTuesday, June 2410:30am - 10:45am PDT
Location3003, Level 3
Design
DES2A: In-memory and Near-memory Computing Circuits
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