Presentation
HIVE: A Hierarchical Inverse Graph Construction Framework for Verilog Code Generation and Compilation Error Correction Using Large Language Models
DescriptionRecent advancements in large language models (LLMs) have shown significant potential in automating chip design, particularly in generating Verilog code from high-level specifications. While much of the existing research focuses on end-to-end generation from specifications to code, there has been limited exploration of the linguistic style of module descriptions and the structured representation of intermediate circuit forms. In this paper, we introduce HIVE, a novel framework that improves Verilog code generation and debugging accuracy by integrating semantic style transfer, graph-structured reasoning and compilation error modification with retrieval augmented generation. The HIVE framework leverages GPT-3.5Turbo-FT and GPT-4Turbo, achieving state-of-the-art performance on both the VerilogEvalv1 and Thakur's benchmarks. Notably, HIVE-GPT3.5Turbo-FT eliminates syntax errors across all test cases in Thakur's benchmark. Furthermore, HIVE-GPT4Turbo achieves a pass rate of 83.3% on the more challenging VerilogEvalv2 benchmark, demonstrating its robustness in generating high-quality Verilog code.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby