Presentation
A Novel Power-gradient-aware Cell Placement Methodology Considering 3D-IC Stacking Thermal Boundary to Achieve Timing and Thermal Co-optimization
DescriptionThermal effects degrade performance by 10%-20% in 3D-IC designs due to dense stacking, making thermal superposition effect crucial for all dies. Without early thermal considerations in cell placement, later modifications are limited. Traditional thermal-aware cell placement is time-consuming and inaccurate, as it iteratively performs thermal simulations to fix hotspots without considering 3D-IC Stacking thermal boundary and timing performance. This paper presents a novel approach to break the thermal superposition loop by redistributing power distribution and inserting appropriately sized white spaces with considering 3D-IC stacking thermal boundary conditions while minimizing timing impact. Run time is significantly improved by simply analyzing power distribution instead of running thermal simulations. Experimental results demonstrate a minimum reduction in hotspot temperatures by 6%, a minimum runtime improvement of 100x, and a minimized timing impact of less than 0.5%.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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