Presentation
Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells
DescriptionThis paper develops a comprehensive placement and routing framework for synthesizing CFET cells to address scaling issues in advanced nodes. We first develop a BFS-based partitioning technique with a heuristic quality maintenance strategy to ensure scalability. Then, we propose a SMT-based placement method that incorporates partial routing for minimum-width placement and in-cell routability. Finally, a progressive metal routing method is proposed to address the challenges of routing resource scarcity. Compared with the state-of-the-art CFET cell generators, experimental results show that our algorithm achieves the optimal cell width for all cells, with 7 out of 30 cells exhibiting smaller widths.
Event Type
Research Manuscript
TimeWednesday, June 2511:30am - 11:45am PDT
Location3006, Level 3