Presentation
TickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector Processor
DescriptionIn modern chips, much of the power is wasted on the power delivery network, causing thermal issues and voltage drops, which reduces the system's reliability. The voltage stacking technique addresses this problem by reusing charge in similar activity circuits. Still, it suffers from stack voltage ripple and power delivery loss due to the current imbalance caused by the activity factor variation in CMOS logic. This work presents a balancing technique that uses clocked differential logic with constant activity factor to eliminate current imbalance on a gate level in an entire SIMD processor datapath. Applied to a voltage
stacked vector processor called TickTockStack, it achieves a 7.6x reduction of stack voltage ripple and a 33.5% smaller power delivery loss compared to the CMOS baseline with an 18.4% area overhead and without a significant impact on the performance.
stacked vector processor called TickTockStack, it achieves a 7.6x reduction of stack voltage ripple and a 33.5% smaller power delivery loss compared to the CMOS baseline with an 18.4% area overhead and without a significant impact on the performance.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby