Presentation
Synthesis of a memristor-transistor single-phase cell library and its use to synthesize logic circuits
DescriptionMemristor, a passive fundamental circuit component, is a promising candidate for implementing logic circuits. Memristors have extremely low areas and are compatible with MOS devices. Recently, exhaustive enumeration was used to identify extremely low-area memristor-transistor logic cells. In this research, we propose the first constructive method for synthesizing such cells with arbitrary numbers of inputs and devices. We also propose methods for cascading these cells to further improve area efficiency and to carry out device-cell co-optimization to improve performance. We use these methods to create a comprehensive library of memristor-transistor logic cells and use this library to synthesize benchmark circuits using ABC. Logic synthesis results show that our cells dramatically reduce the area for large logic blocks --- around 53% over CMOS cells and 25% over MRL (a logic style that uses memristor-only cell+CMOS inverters) and provide moderate power consumption.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby
DES5: Emerging Device and Interconnect Technologies