Presentation
IM-DSE: Intelligent Muti-target Design Space Exploration for BNN Accelerators in FPGAs
DescriptionBinary Neural Networks (BNNs) are highly effective for image classification and recognition tasks, particularly on power-constrained FPGAs, which are commonly deployed on edge platforms. The FINN framework, a widely used solution, leverages a streaming architecture and a set of novel optimizations to map BNNs onto FPGAs efficiently. However, its design space exploration capabilities remain limited, often leading to suboptimal configurations. To address this, we propose the IM-DSE strategy, a novel multi-target design exploration framework. IM-DSE introduces a multi-objective optimization scheme to identify superior design points by constraining both throughput and Look-Up Table (LUT) consumption. It incorporates an accurate LUT model and a Transferring-Computation (TC) model, which predict LUT usage and processing cycles as functions of the number of SIMDs and PEs per layer. Additionally, IM-DSE employs an intelligent search strategy to efficiently explore optimal accelerator configurations under given constraints. Experimental results demonstrate that, at a target cycle of 1000, IM-DSE achieves an average improvement of 61.72% (up to 87.67%) in energy efficiency and 60.05% (up to 84.42%) in LUT utilization efficiency (FPS/LUT) compared to the state-of-the-art FINN framework across varying LUT constraints.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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