Presentation
One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
DescriptionGray code, a voltage-level-to-data-bit translation scheme, is widely used in QLC SSDs. However, it causes the four data bits in QLC to exhibit significantly different read and write performance with up to 8x latency variation, severely impacting the worst-case performance of QLC SSDs. Although the state-of-the-art approach combines multiple Gray codes to address this, it requires additional circuit overhead and introduces extra programming latency. Our preliminary experiments have identified the root cause of the performance degradation as the unidirectional programming method. This method always programs data into fast bits first then slow bits, leading to poor performance when hot data arrives after cold data.
In this paper, we propose BDP, a novel Bi-Directional Programming scheme that combines both the normal (forward) and reverse programming directions. To avoid extra circuit overhead introduced by multiple Gray codes, we first conduct a theoretical analysis of the ideal performance of various Gray codes to select the most suitable one for the BDP scheme. Second, we introduce a hotness-aware data allocation scheme to judiciously manage hot and cold data by assigning them to the fast and slow bits of QLC, respectively. Third, we propose a background data migration strategy to prevent sharp performance declines when data temperature changes. BDP is integrated into FTL (Flash Translation Layer) and allows the flash controller to enable runtime programming direction arbitration. Experimental results show that BDP outperforms the state-of-the-art solution, achieving an average 26.2% reduction in read latency and an average 50.3% reduction in program latency.
In this paper, we propose BDP, a novel Bi-Directional Programming scheme that combines both the normal (forward) and reverse programming directions. To avoid extra circuit overhead introduced by multiple Gray codes, we first conduct a theoretical analysis of the ideal performance of various Gray codes to select the most suitable one for the BDP scheme. Second, we introduce a hotness-aware data allocation scheme to judiciously manage hot and cold data by assigning them to the fast and slow bits of QLC, respectively. Third, we propose a background data migration strategy to prevent sharp performance declines when data temperature changes. BDP is integrated into FTL (Flash Translation Layer) and allows the flash controller to enable runtime programming direction arbitration. Experimental results show that BDP outperforms the state-of-the-art solution, achieving an average 26.2% reduction in read latency and an average 50.3% reduction in program latency.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby