Presentation
ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family Resilient to DPA Attack and Reverse Engineering
DescriptionAttacks that exploit side-channel information inevitably emitted during hardware encryption pose a significant threat to hardware security, as they can extract sensitive user information. Additionally, fabless companies often rely on specific foundries for chip manufacturing, which increases the risk of information leakage from untrusted fabs. Circuit design is also vulnerable to replication threats due to sophisticated reverse engineering techniques. To address these challenges, this paper proposes Fast Post-Manufacturing Programmable Camouflaged (FP2C) Logic. Implemented as a flip-flop with embedded FP2C logic, this design exclusively utilizes regular threshold voltage (RVT) transistors, allowing integration into standard cell libraries and enabling automated digital circuit design through EDA tools. By applying a post-programming code after manufacturing, FP2C logic safeguards against information leakage from untrusted fabs and strengthens security by imposing an additional overhead for attackers attempting to obtain the programming code.
The proposed FP2C Logic-embedded Flip-Flop (FP2C Logic-eFF) was designed in a 28nm CMOS process, achieving a 67% reduction in cell area compared to Post-Manufacturing Programmable (PMP) -TVD logic cell on the same technology node. To demonstrate the feasibility of implementing digital systems with FP2C Logic, the Advanced Encryption Standard (AES) was designed as a representative cryptographic IP. Tests on the AES-128 module demonstrated that a standard cell-based AES design exposes the secret key at 21k power traces, while FP2C logic-eFF-based AES has been proven to extract only one byte of key extraction at 100k traces and achieves an additional 81.3-bit security strength.
The proposed FP2C Logic-embedded Flip-Flop (FP2C Logic-eFF) was designed in a 28nm CMOS process, achieving a 67% reduction in cell area compared to Post-Manufacturing Programmable (PMP) -TVD logic cell on the same technology node. To demonstrate the feasibility of implementing digital systems with FP2C Logic, the Advanced Encryption Standard (AES) was designed as a representative cryptographic IP. Tests on the AES-128 module demonstrated that a standard cell-based AES design exposes the secret key at 21k power traces, while FP2C logic-eFF-based AES has been proven to extract only one byte of key extraction at 100k traces and achieves an additional 81.3-bit security strength.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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