Presentation
Mr.TPL: A New Multi-pin Routing Method for Triple Patterning Lithography
SessionAll You Can Route Buffet
DescriptionTriple patterning lithography (TPL) has been recognized as one of the most promising solutions to print critical features in advanced technology nodes. A critical challenge within TPL is the effective assignment of the layout to masks. Recently, various layout decomposition methods and TPL-aware routing methods have been proposed to consider TPL. However, these methods typically result in numerous conflicts and stitches, and are mainly designed for 2-pin nets. This paper proposes a multi
pin net routing method in triple patterning lithography, called Mr.TPL. Experimental results demonstrate that Mr.TPL reduces color conflicts by 81.17%, decreases stitches by 76.89%, and achieves up to 5.4× speed improvement compared to the state-of the-art TPL-aware routing method.
pin net routing method in triple patterning lithography, called Mr.TPL. Experimental results demonstrate that Mr.TPL reduces color conflicts by 81.17%, decreases stitches by 76.89%, and achieves up to 5.4× speed improvement compared to the state-of the-art TPL-aware routing method.
Event Type
Research Manuscript
TimeTuesday, June 242:30pm - 2:45pm PDT
Location3004, Level 3
EDA
EDA7: Physical Design and Verification