Presentation
Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing
DescriptionMicro base stations, with limited antennas and extensive deployment, require scaled-down hardware. Traditional Software Defined Radio (SDR) solutions (e.g., CPU, manycore systems, GPU) offer flexibility but incur high area and power costs, while DSP lacks efficient acceleration for smaller configurations. The key challenge is achieving minimal area and power overhead while meeting 5G requirements. This paper presents a hardware-software co-designed architecture, Sayram, which minimizes overhead for 5G physical layer processing. Sayram integrates an instruction fusion mechanism, along with the compiler for simplified programming, and a Vector Indirect Addressing Memory (VIAM) to minimize memory access cycles, boosting overall processor efficiency. Operating at 1 GHz, Sayram achieves 158 Gops with a 1.18 mm² area, supporting 2T2R and 4T4R PUSCH processing in single-core and dual-core modes, respectively. Evaluations show that Sayram's area efficiency is 48×, 180×, and 2591× higher than manycore, DSP, and CPU architectures, with power efficiency improvements of 54×, 362×, and 4400×, respectively.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby