Presentation
Synergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing Optimization
DescriptionAs modern field-programmable gate arrays (FPGAs) continue to grow in complexity, systems featuring multi-die devices connected through time-division multiplexing (TDM) techniques have become increasingly common for implementing large-scale designs. FPGA designs are meticulously partitioned at the die-level for prototyping in modern emulation systems. A die-level router for multi-FPGA systems aims to find routing paths between dies according to the partitioning results. Conventional FPGA-level routers often result in a large critical connection delay that impacts the whole design's frequency. Additionally, the excessive use of super long lines (SLLs) between neighboring dies leads to substantial routing congestion, causing the failure of the routing progress. To tackle these issues, we propose an effective and efficient die-level router for multi-FPGA systems, optimizing routing topology and the TDM ratio. Experimental results on the benchmarks from the die-level routing contest 2023 demonstrate 7.6% better critical connection delay with a 5.761x speed-up compared to the state-of-the-art router.
Event Type
Research Manuscript
TimeTuesday, June 245:15pm - 5:30pm PDT
Location3004, Level 3
EDA1: Design Methodologies for System-on-Chip and 3D/2.5D System-in Package