Presentation
GLiTCH : GLiTCH induced Transitions for Secure Crypto-Hardware
DescriptionConventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time control, which is cast as a Geometric Programming formulation. We develop a framework, GLiTCH, for glitch manipulation that is guided by functional and timing simulations. The framework is evaluated on popular cipher designs like AES, CLEFIA, and SM4. Our findings illustrate up to 52.82% improvement in the Guessing Entropy for a 38.74% area overhead on average across the evaluated ciphers.
Event Type
Research Manuscript
TimeMonday, June 2311:45am - 12:00pm PDT
Location3004, Level 3
EDA
EDA3: Timing Analysis and Optimization