Presentation
SCMG: Scalable and Configurable FPGA-based Multiplier Generator using Integer Linear Programming
DescriptionHigh-performance multipliers are critical components across numerous applications. While FPGAs utilize DSP blocks for efficient multiplication, their limited quantity, fixed placement, and potential for timing closure issues necessitate the exploration of alternative solutions. Logic-based softcore multipliers offer a promising solution, but existing FPGA-oriented implementations predominantly focus on heuristic small-scale multipliers, lacking the scalability and holistic optimization required for larger instances. Moreover, prior designs neglect the tunable balance between latency and resource utilization, employing fixed logic depth and cost, thereby limiting their adaptability to different scenarios. This paper introduces SCMG, a Scalable and Configurable FPGA-based Multiplier Generator that employs Integer Linear Programming (ILP) to overcome these limitations. SCMG offers flexible configuration of multiplier size and logic levels, enabling application-specific performance-prioritized or cost-prioritized optimization. The ILP-based approach efficiently generates optimal designs tailored to specific resource constraints and performance targets. Furthermore, SCMG supports the efficient generation for approximations, providing a valuable option for fault-tolerant applications. Experimental results demonstrate SCMG's significant advantages over AMD Vivado's built-in multiplier IP, achieving up to 23.3% area reduction, 15.6% latency improvement, and 24.5% energy efficiency enhancement. The tool is open-sourced to promote further research and development in this area.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby