Presentation
Clearance-Constrained PCB Global Placement with Heterogeneous Components
DescriptionThe complexity of design rules and intense time-to-market demands have made auto-placement tools essential for advanced printed circuit board (PCB) designs. This paper presents a novel PCB placement framework to handle pad-to-pad clearance constraints and heterogeneous components to address these challenges. Unlike existing academic placers, our framework focuses on the following key features: a wire-area model to account for various routing resource needs between power and signal nets, a pad-to-pad clearance model to minimize spacing violations, and a two-sided, pad-type-aware density model to reduce component and pad overlap. We further develop a quadratic programming-based legalizer to resolve constraint violations among components of varying shapes. Experimental results show the effectiveness and efficiency of our framework, surpassing two state-of-the-art academic placers in post-routing quality on both academic and industrial benchmarks.
Event Type
Research Manuscript
TimeTuesday, June 2410:30am - 10:45am PDT
Location3004, Level 3
EDA
EDA7: Physical Design and Verification