Presentation
Accuracy Is Not Always We Need: Precision-aware Bayesian Yield Optimization
DescriptionIntegrated circuit yield optimization plays a vital role in ensuring reliable semiconductor manufacturing. Current approaches allocate equal computational resources across design candidates causing low efficiency. To this end, we introduce a novel precision-aware yield optimization framework that intelligently adapts computational resource allocation based on the design candidate's predicted performance. Our approach moves beyond simple simulation counting by incorporating a Figure of Merit as a continuous quality metric. By combining a continuous autoregression model to characterize the relationship between yield and precision levels with a sophisticated multi-fidelity acquisition strategy, our framework achieves optimal resource distribution, reducing simulation costs by over 10x.
Event Type
Research Manuscript
TimeMonday, June 232:30pm - 2:45pm PDT
Location3004, Level 3
EDA
EDA8: Design for Manufacturing and Reliability