Presentation
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation
DescriptionDespite of the greater energy efficiency, it remains challenging for high-level users to customize graph processing accelerators on FPGAs. This paper introduces Graphitron, a domain-specific language for graph processing that customizes FPGA-based accelerators for various algorithms while hiding the complexities of low-level FPGA designs from users. Graphitron defines vertex and edge as primitive data types, which simplify the description of operations on edges and vertices in general graph processing algorithms. Further, Graphitron compiler leverage graph semantic information inherent to graph processing to apply typical hardware optimization techniques, including pipelining, data shuffling, caching and burst accesses, on the generated accelerators for higher performance. Our experiments show that Graphitron offers exceptional flexibility in algorithm description and significantly enhances the productivity of graph processing accelerator designs. Graphitron-crafted accelerators generally achieve comparable performance to those generated by pre-defined templates and even outperform on benchmarks that can benefit from the flexible graph processing architectures.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby