Presentation
Scalar Runahead
DescriptionRunahead execution is a technique to mask memory latency caused by irregular memory access. Runahead pre-executes the application code to achieve high prefetch accuracy; however, this technique has been limited to Out-of-Order (OoO) and Superscalar In-Order (Super-InO) cores. For implementation in Scalar In-Order (Scalar-InO) cores the challenges of area-constraint and energy-constraint remain.
Here, we build the first Scalar-InO processor featuring runahead, SR, into an open-source SoC, from the microarchitecture to the ISA. Through this deployment, we establish that implementing SR in Scalar-InO cores is possible, with minimal area and power overheads, while still achieving high performance. We also present an adaptive prefetch method to further improve performance. In the evaluation, we demonstrate the performance benefits and give the power and area overheads of SR.
Here, we build the first Scalar-InO processor featuring runahead, SR, into an open-source SoC, from the microarchitecture to the ISA. Through this deployment, we establish that implementing SR in Scalar-InO cores is possible, with minimal area and power overheads, while still achieving high performance. We also present an adaptive prefetch method to further improve performance. In the evaluation, we demonstrate the performance benefits and give the power and area overheads of SR.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby