Presentation
DSPlacer: DSP Placement for FPGA-based CNN accelerator
DescriptionDeploying convolutional neural networks (CNNs) on Field Programmable Gate Arrays (FPGAs) presents challenges in achieving optimal timing closure due to placement's impact on clock frequency and throughput. We propose DSPlacer, a novel framework for diverse CNN accelerator architectures, integrating techniques such as GCN-based DSP identification, DSP graph construction, min-cost-flow assignment, and ILP-based cascade legalization. DSPlacer ensures a compact layout while preserving direct datapath connections. Evaluated against AMD Xilinx Vivado 2020.2 and AMF-Placer 2.0, DSPlacer improves Worst Negative Slack (WNS) by 32% and 65%, demonstrating its effectiveness and scalability.
Event Type
Research Manuscript
TimeWednesday, June 2510:30am - 10:45am PDT
Location3006, Level 3
EDA
EDA7: Physical Design and Verification