Presentation
ConNAS4ML: Constraint-Aware Differentiable Neural Architecture Search for Efficient FPGA Deployment
DescriptionLow-latency machine learning (ML) on resource-limited FPGAs is critical for applications like high-energy physics and autonomous systems. However, balancing latency, accuracy, and hardware constraints remains a challenge. Existing methods often adopt a software-first approach, relying on proxy metrics and overlooking direct hardware considerations, which leads to suboptimal resource usage and costly deployment adjustments. We propose ConNAS4ML, a constraint-aware differentiable neural architecture search (DNAS) framework. By modeling resource usage as a continuous function with a novel quadratic exterior penalty loss, ConNAS4ML enables fast, single-stage, gradient-based optimization under hardware constraints. Experiments demonstrate that ConNAS4ML achieves an average of up to 59.15% FPGA resource reduction with minimal performance degradation, enabling practical deployment in resource-constrained environments.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby