Presentation
Hypnos: Memory Efficient Homomorphic Processing Unit
DescriptionFully Homomorphic Encryption (FHE) introduces a novel paradigm in privacy-preserving computation, extending its applicability to various scenarios. Operating on encrypted data, however, imposes significant computational challenges, particularly elevating data transmission and memory access demands. Consequently, developing an efficient system storage architecture becomes vital for FHE-specific architectures. Traditional FHE accelerators use a Host+ACC topology, often focusing on enhancing computational performance and efficient use of on-chip caches, with the assumption that very large volumes of encrypted data are already present in the accelerator's memory while neglecting the inevitable high cost of data transfer. In this paper, we propose Hypnos—a memory-efficient homomorphic encryption processing unit. In Hypnos, we abstract operators from FHE schemes into commands suitable for memory-efficient processing units and combine them with a homomorphic encryption paged memory management system designed for memory access, significantly reducing the memory access and execution time of homomorphic encryption applications. We implement Hypnos on the QianKun FPGA Card and highlight the following results: (1) outperforms SOTA ASIC and FPGA solutions by 2.58x and 4.43x; (2) the communication overhead is reduced by 3.78x compared to traditional architectures; (3) up to 27.6x and 19.06x energy efficiency improvement compared to ASIC-based CraterLake and FPGA-based Poseidon for ResNet-20 respectively.
Event Type
Research Manuscript
TimeMonday, June 234:30pm - 4:45pm PDT
Location3002, Level 3
DES1: SoC, Heterogeneous, and Reconfigurable Architectures
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