Presentation
Place-and-Route for Photonic Integrated Circuits using Industry-Standard EDA Tools
DescriptionRapid advances of Electro-Photonic Integrated Circuits (EPICs), across various material platforms, are driving the integration of numerous devices into complex heterogeneous systems. A key application is high-bandwidth communications for distributed computing. While manufacturing Photonic Integrated Circuits (PICs) leverages standard VLSI fabrication processes for electronic ICs, the PIC design ecosystem still lags behind the maturity of Electronic Design Automation (EDA) tools.
To address these challenges, we introduce a publicly available, fully automated Photonic Place-and-Route (PnR) flow that operates across different material platforms and integrates seamlessly with industry-standard EDA tools. Our contributions include:
(1) Photonic-to-electronic PnR mapping: Techniques to accommodate the distinct characteristics of photonic routing, such as waveguide bending constraints and optical metric mapping for performance optimization.
(2) Comprehensive verification suite: A suite comprising Design Rule Check (DRC), Layout-vs-Schematic (LVS), and Parasitic Extraction (PEX) to ensure manufacturing compliance and accurate simulation using compact models (VerilogA/SPICE) of Electro-Optical devices.
(3) Reference designs for multiple applications: Demonstrations include (a) high-bandwidth optical switch fabrics and (b) timing-optimized optical trees, that showcase the flexibility and performance of our Photonic PnR solution (completion of 1000 devices in 20 & 50 minutes for unconstrained & constrained respectively).
This integrated approach enables more efficient design and optimization of EPICs, supporting future advances in electro-photonic systems.
To address these challenges, we introduce a publicly available, fully automated Photonic Place-and-Route (PnR) flow that operates across different material platforms and integrates seamlessly with industry-standard EDA tools. Our contributions include:
(1) Photonic-to-electronic PnR mapping: Techniques to accommodate the distinct characteristics of photonic routing, such as waveguide bending constraints and optical metric mapping for performance optimization.
(2) Comprehensive verification suite: A suite comprising Design Rule Check (DRC), Layout-vs-Schematic (LVS), and Parasitic Extraction (PEX) to ensure manufacturing compliance and accurate simulation using compact models (VerilogA/SPICE) of Electro-Optical devices.
(3) Reference designs for multiple applications: Demonstrations include (a) high-bandwidth optical switch fabrics and (b) timing-optimized optical trees, that showcase the flexibility and performance of our Photonic PnR solution (completion of 1000 devices in 20 & 50 minutes for unconstrained & constrained respectively).
This integrated approach enables more efficient design and optimization of EPICs, supporting future advances in electro-photonic systems.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby