Presentation
Boolean Reasoning Guided Ungrouping
DescriptionUngrouping is a key step in design implementation. This step is tasked to dissolve selected hierarchical boundaries in order to unlock more optimization opportunities and logic sharing.
Determining the right amount of ungrouping is an important and challenging problem which requires new and innovative technologies in logic synthesis.
On the one hand, ungrouping too much may impact the verifiability of the implemented netlist, reduce the scalability of synthesis, and degrade the Quality of Results (QoR).
On the other hand, not ungrouping enough may fail to catch many optimization opportunities and degrade QoR even further.
Existing solutions are mainly guided by comparing the size of the children and parent hierarchies to be ungrouped.
In this paper, we propose a novel ungrouping flow based on Boolean reasoning.
We guide ungrouping with formal reasoning engines, such as Boolean SATisfiability (SAT), considering logic sharing, connectivity, and Boolean optimization opportunities identified across the design.
We show how this flow unlocks more QoR, keeps verification complexity contained, and preserves the most advantageous hierarchical boundaries for synthesis.
We integrate our novel ungrouping flow within an industrial synthesis tool, showing significant QoR improvement over the state-of-the-art solutions.
Determining the right amount of ungrouping is an important and challenging problem which requires new and innovative technologies in logic synthesis.
On the one hand, ungrouping too much may impact the verifiability of the implemented netlist, reduce the scalability of synthesis, and degrade the Quality of Results (QoR).
On the other hand, not ungrouping enough may fail to catch many optimization opportunities and degrade QoR even further.
Existing solutions are mainly guided by comparing the size of the children and parent hierarchies to be ungrouped.
In this paper, we propose a novel ungrouping flow based on Boolean reasoning.
We guide ungrouping with formal reasoning engines, such as Boolean SATisfiability (SAT), considering logic sharing, connectivity, and Boolean optimization opportunities identified across the design.
We show how this flow unlocks more QoR, keeps verification complexity contained, and preserves the most advantageous hierarchical boundaries for synthesis.
We integrate our novel ungrouping flow within an industrial synthesis tool, showing significant QoR improvement over the state-of-the-art solutions.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby