Presentation
Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet Integration
DescriptionThe design of three-dimensional integrated circuits (3D-ICs) is at the forefront for cost-effective and high-performance computing systems. 3D systems enable the vertical stacking of multiple chiplets, reducing areas and interconnection lengths. On the other hand, the floorplanning of such systems requires more computational resources. To address this problem, we propose Daedalus, a framework supporting the design of 3D-ICs. Daedalus provides an environment where multiple design constraints can be enforced, enabling to find the optimal configuration by exploring the solution space. The experimental results show the effectiveness of our method in solving floorplanning with increasing complexity in a timely manner.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby