Presentation

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Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories

SessionShaping Tomorrow: Co-Designing Emerging Technologies for Computing and Beyond

DescriptionThis work presents a novel Monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates. By integrating BEOL-compatible n-type (W-doped In₂O₃) and p-type (SnO) amorphous oxide semiconductor (AOS) transistors, Si SRAM configuration bits are substituted with a less leaky equivalent, programmable at logic-compatible voltages. Using AOS pass gates reduces the overhead of reconfigurable circuits by mapping FPGA switch block and connection block matrices above configurable logic blocks, thereby increasing the proximity of logic elements. Modifying the Verilog-to-Routing suite demonstrates that an AOS-based M3D FPGA can dramatically improve FPGA power, performance, and footprint.

Authors

Faaiq Waqar

Georgia Institute of Technology

Jiahao Zhang

University of California, Los Angeles

Anni Lu

Georgia Institute of Technology

Zifan He

University of California, Los Angeles