Presentation
Accelerating device level synthesis of binarized convolutional neural networks
DescriptionThis paper presents an Electronic Design Automation (EDA) methodology for synthesizing mixed-signal Binarized Neural networks (BNNs) at CMOS device level. Despite the advances in Convolutional Neural Networks (CNN) high level frameworks with quantization capabilities, and contrary to digital design, there are not tools to translate such networks into mixed-signal electronic circuits. Such circuits could however offer enhanced performance regarding power dissipation or computation resources trade-offs compared to digital ones. The proposed methodology translates high level CNNs descriptions to device level designs, within the mixed-signal design cycle, enabling efficient iteration across architectural variants. The methodology is validated through SKILL language implementation, demonstrating synthesis of a compact MNIST neural network.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
Similar Presentations