Presentation
TiLeR: Hardware-In-The-Loop Mitigation of Software Timing Side-Channel Vulnerabilities
DescriptionTiming attacks exploit variations in a program's execution times to extract sensitive information from the program (e.g. encryption keys, additive manufacturing pathways).
Typical solutions to timing side-channel vulnerabilities attempt to balance the execution time of the sensitive code for different control flow paths to eliminate the timing leakage (without much consideration given to the underlying hardware).
We propose TiLeR, a novel joint hardware-software methodology for mitigating timing side-channel vulnerabilities that utilizes timing values from real embedded devices. We implement/evaluate TiLeR on four embedded devices using six software benchmarks and observe significant post-fixed codes' performance advantage compared to constant-time programming.
Typical solutions to timing side-channel vulnerabilities attempt to balance the execution time of the sensitive code for different control flow paths to eliminate the timing leakage (without much consideration given to the underlying hardware).
We propose TiLeR, a novel joint hardware-software methodology for mitigating timing side-channel vulnerabilities that utilizes timing values from real embedded devices. We implement/evaluate TiLeR on four embedded devices using six software benchmarks and observe significant post-fixed codes' performance advantage compared to constant-time programming.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby