Presentation
Optimal Front vs Back-side Signal Allocation for PPA Improvements in Advanced CMOS Featuring Back-side Metal Interconnects
DescriptionThis study explores the potential of Back-side Contact (BSC) technology for enhancing Power, Performance, and Area (PPA) in integrated circuits. Through Design-Technology-Circuit co-optimization (DTCO) experiments on a 32-bit RISC-V core, the research demonstrates significant PPA gains by optimizing front and back-side metal stack and layer purpose allocation. Key findings include an average 2.7% power reduction per added back-side layer for clock routing, a 5.5% frequency improvement with combined front and back-side clock routing, and up to 17% power reduction or 10% frequency increase through DTCO-based metal stack optimization for low-power and high-performance targets, respectively.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby
DES5: Emerging Device and Interconnect Technologies