Presentation
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
DescriptionHardware description languages (HDLs), like VHDL, pose challenges for large language models (LLMs) due to limited data, syntactic complexity, and mismatched vocabularies. To address these, we introduce the VHDL-IR dataset with diverse parallel data pairs and develop a custom retriever to align VHDL syntax, functionality, and natural language. Our Divide-Retrieve-Conquer (DiReC) strategy enhances LLM performance by modularizing tasks, retrieving relevant contexts, and integrating results for accurate outputs. Experiments show up to 20% improvement in code generation and 12% in summarization over standard RAG, demonstrating DiReC's effectiveness while identifying areas for further VHDL-focused research.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby