Presentation
Transistor Placement Routability Prediction for Standard Cell Design
DescriptionStandard cells are the core of digital Very Large Scale Integration designs, but advancements beyond the 7nm node have made layout design more challenging due to complex rules and limited routing resources. Effective placement is crucial, as minor transistor order changes can affect routability. Sequential place-and-route frameworks often expend significant resources on unroutable placements. To enhance efficiency, predicting placement routability before routing is vital. This paper proposes a transistor placement routability predictor using image recognition. Tested on 690 cells, it achieves prediction accuracies of 96.32\% for single-height and 93.51\% for double-height configurations.
Event Type
Networking
Work-in-Progress Poster
TimeMonday, June 236:00pm - 7:00pm PDT
LocationLevel 2 Lobby