Presentation
MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations
DescriptionIn this paper, we propose MOOPSE (Matrix multiply Operation Optimization with Partially-Shared high-radix booth Encoder), a novel matrix multiply unit (MMU) used in processor cores. A key feature of MOOPSE is the use of high-radix Booth encoders, which reduces the area of fused multiply add (FMA) units, improving the area-efficiency of MMUs. Although high-radix Booth encoders are rarely used in conventional FMA units due to performance, power, and area overheads, our MOOPSE solves this issue by sharing main internal components of Booth encoders between multiple FMA units. Our experimental results show that MOOPSE shows respective improvements of up to 9%, 21%, 19%, and 16% in performance per area, dynamic power efficiency, leakage power efficiency, and area overhead compared to the state-of-the-art MMU.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby