Presentation
An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
DescriptionThe reconfigurable platform offers possibilities for identifying the bit-level unstructured redundancy during inference with different DNN models. Researchers noticed significant progress in value-aware accelerators on ASICs, yet we are concerned about the few studies on FPGAs. This paper observed the limitations of implementing bit-level sparsity optimizations using FPGA and proposed a software/architecture co-design solution. Specifically, by introducing LUT-friendly encoding with adaptable granularity and hardware structure supporting multiplication time uncertainty, we achieved a better trade-off between potential redundancy and accuracy with compatibility and scalability. Experiments show that under accurate calculation, PEs are up to 2.2× smaller than bit-parallel ones, and our design boosts performance by 1.04× to 1.74× and 1.40× to 2.79× over bit-parallel and Booth-based designs, respectively.
Event Type
Research Manuscript
TimeWednesday, June 255:15pm - 5:30pm PDT
Location3000, Level 3
AI
AI3: AI/ML Architecture Design
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