Presentation
Automated Hardware-Mapping Co-Design for Neural Network Acceleration with Single-Step Reinforcement Learning
DescriptionDesigning deep neural network (DNN) accelerator configurations is challenging due to the vast design space encompassing hardware resources and mapping strategies. We present CORE, a novel hardware and mapping CO-design methodology using single-step REinforcement learning to optimize spatial DNN accelerators for simulation-based metrics. CORE employs a policy neural network to generate near-optimal joint distributions for sampling design choices. A scaling graph-based decoding method captures dependencies between design choices and maps them into accelerator configurations. Guided by configuration simulation, the policy NN is updated with an adaptive reward mechanism to penalize invalid designs and accelerate convergence. Experimental results show that CORE improves latency and latency-area-sum by over 15× compared to baseline methods while reducing the number of sampled designs.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby