Presentation
Early Mismatch Detection in Analog Layout Using PLS Netlist
DescriptionMatching of devices and circuit elements is of utmost importance in Analog integrated circuit designs. The matching checks are mostly done manually and is on discretion of analog layout designers. These mismatches impact the simulation results, leading to a long iterative process to close the design and there is high probability that some mismatches could get missed. This paper proposes an innovative automated approach using standard tools (Cadence Virtuoso and python script) to detect and address potential device matching issues in analog layouts. This is a technology independent approach. We validated it in 90nm technology using eNVM test case. We observed potential matching issues in layout due to variations in extracted parameters like SCI parameter (which is related to WPE) and STI parameters (sa & sb). Mapping these variations to the layout helped in reducing potential device mismatches. With the help of k-means clustering algorithm, python scripting aids in identifying outlier devices. The proposed methodology will help the layout engineer to ensure that layout matches correctly before sending the netlist for simulation, which will shorten the time needed to complete the design.
Event Type
Networking
Work-in-Progress Poster
TimeSunday, June 226:00pm - 7:00pm PDT
LocationLevel 3 Lobby
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